1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to a process for plasma etching of a spin-on glass (SOG) layer used in forming a highly effective passivation layer.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements called interconnect lines (interconnects). Interconnects are patterned from layers of electrically conductive materials (e.g., aluminum, doped polysilicon, etc.) formed on the surface of a silicon wafer. Multiple layers (or levels) of closely-spaced interconnects allow an increase in the density of devices formed on semiconductor wafers. Electrical separation of stacked interconnect layers is achieved by placing an electrically insulating material (i.e., interlevel dielectric layer) between the vertically spaced interconnect layers. Following patterning of the final interconnect layer, a passivation layer is deposited over the entire top surface of the integrated circuit. This passivation layer protects the integrated circuit from mechanical and chemical damage during assembly and packaging operations.
Interconnects in the final interconnect layer are commonly patterned from aluminum or aluminum alloys. The relatively low melting point of aluminum (and aluminum alloys) precludes the formation of passivation layers with many standard techniques. Common dielectric materials used for passivation layers include phosphorus-doped silicon dioxide (oxide) and silicon nitride. Phosphorus-doped oxide is typically deposited over aluminum interconnects of a final interconnect layer using a low-temperature chemical vapor deposition (CVD) process. Silicon nitride is typically deposited over aluminum interconnects of a final interconnect layer using a plasma enhanced CVD (PECVD) process.
In general, thicker passivation layers provide better protection of underlying structures. However, when the thickness of a passivation layer becomes appreciable with respect to the distance between closely-spaced interconnects in the final interconnect layer, air pockets (i.e., voids) may form between the closely-spaced interconnects during the formation of the passivation layer. One way to achieve a relatively thick passivation layer while avoiding the void creation problem is to employ a layer of a spin-on glass (SOG) material interposed between two layers of a common CVD dielectric material used for passivation.
SOG is becoming a popular interlevel dielectric material. Common SOG materials include silicates or siloxanes mixed in alcohol-based solvents. Siloxane-based SOG materials have organic methyl (CH.sub.3) or phenyl (C.sub.6 H.sub.5) groups added to improve cracking resistance. Applied to a wafer surface in liquid form, SOG materials typically flow over and fill narrow spaces between interconnects without creating voids. In addition, SOG materials produce a surface smoothing effect at vertical edges. SOG materials are thus frequently used to planarize the upper surface of interlevel dielectric layers.
During a typical SOG application, a layer of a liquid SOG material is first applied over the surface of a silicon wafer. The SOG layer is then cured by heating the wafer in a furnace. A typical SOG curing process includes two heating steps. A first heating step is carried out at a relatively low temperature (e.g., 150.degree.-250.degree. C. for 1-15 minutes in air) to drive the solvent out of the SOG layer. A second heating step is then performed at a higher temperature (e.g., 400.degree.-425.degree. C. for 30-60 minutes in air) to drive out water formed during polymerization of the SOG material. The remaining solid SOG film exhibits dielectric properties similar to those of an oxide film.
SOG materials have many drawbacks, however. When an SOG layer is formed to the thickness required of an interlevel dielectric, it exhibits an intolerable degree of cracking. In addition, adhesion failures are often observed at interfaces between SOG layers and metal interconnects. Delamination problems (i.e., adhesion failures at interfaces between SOG layers and overlying and underlying dielectric layers) have also been experienced. Further, the density of SOG oxide is relatively low, leading to a high degree of water sorption. Diffusion of water from the SOG material into contact regions results in high resistance failures of electrical contacts formed in holes etched through the interlevel dielectric layers between interconnect levels.
In order to reduce the problems associated with SOG materials, many surface planarization methods employ an SOG layer interposed between two other dielectric layers. The other dielectric layers are used to reduce the SOG water sorption problem and are typically deposited using chemical vapor deposition (CVD) techniques. The other dielectric layers encapsulate the SOG layer, reducing the diffusion of water from the SOG material into contact regions. Being relatively thin and substantially conformal, the other dielectric layers do not significantly enhance the planarity of the surface topography. There are two common variations of the dielectric-SOG-dielectric planarization approach: (i) etchback SOG, and (ii) non-etchback SOG. See, S. Wolf, Silicon Processing for the VLSI Era, Vol. 2, pp. 233-236.
In the non-etchback SOG variation of the dielectric-SOG-dielectric planarization approach, special non-organic, crack-resistant silicate SOG materials are used. Silicate-based SOG materials do not absorb moisture as readily as siloxane-based SOG materials. In a typical application of the non-etchback SOG approach, a first CVD dielectric layer is initially formed over an interconnect level arranged on a surface of a silicon wafer. A layer of silicate-based SOG is then applied over the first CVD dielectric layer and cured using a heating process. A second CVD dielectric layer is then formed over the SOG layer.
The major drawback of the non-etchback SOG variation of the dielectric-SOG-dielectric structure is that it does not prevent water in the SOG layer from diffusing to contact regions when electrical contacts are formed in vias. In the widely adopted etchback SOG variation of the dielectric-SOG-dielectric planarization method, a layer of a siloxane-based SOG material is applied over a first CVD dielectric layer. Portions of the SOG layer and the uppermost layer of the first CVD dielectric layer are then removed using a dry plasma etch process prior to deposition of a second CVD dielectric layer. In this manner, SOG material is removed in areas where vias will be etched and contacts formed. This prevents any water in the SOG layer from diffusing into the contact regions. SOG remains only in troughs or valleys between closely-spaced interconnects and adjacent to the vertical steps between widely-spaced interconnects. The remaining SOG substantially fills troughs or valleys between closely-spaced interconnects, and reduces sudden changes in elevation adjacent to widely-spaced interconnects.
In a passivation layer application of dielectric-SOG-dielectric structures, delamination problems (i.e., adhesion failures at interfaces between the SOG layer and overlying and underlying dielectric layers) experienced with the nonetchback SOG approach have prompted the use of the etchback SOG approach. One drawback to the etchback SOG approach, however, is that the etch process used to remove portions of the SOG layer also removes any exposed portions of the first CVD dielectric layer. In order to remove enough of the SOG layer to prevent delamination, a significant portion of the first dielectric layer is exposed and removed. As a result, the thickness of the first dielectric layer is undesirably reduced.
It would thus be desirable to have an etchback SOG process which etches an SOG layer at a faster rate than the rate at which it etches an underlying first dielectric layer (i.e., an SOG plasma etch process selective to the first dielectric layer). Such a plasma etch process would remove enough of the SOG layer to prevent delamination problems associated with SOG layers interposed between dielectric layers without significantly reducing the thickness of the first dielectric layer.